Title :
Performances of the AES design in 0.18μm CMOS technology
Author :
Mestiri, Hassen ; Machhout, Mohsen ; Tourki, Rached
Author_Institution :
Fac. of Sci. of Monastir, Electron. & Micro-Electron. Lab. (E. μ. E. L), Monastir, Tunisia
Abstract :
The Advanced Encryption Standard (AES) has been studied by designers with the goal to improve its performances in terms of area, power consumption and frequency. In this paper, we present the implementation details of the AES encryption 128-bit, the MixColumns transformation and the SubBytes transformation. The latter can be implemented using a multi-stage PPRM architecture and composite field arithmetic in GF(((22)2)2). In addition, the MixColumns transformation is used in two architectures. The AES algorithm is implemented using 1.8V 0.18μm Complementary Metal Oxide Semiconductor (CMOS) technology. A low power consumption of 24.92 μW at 10 MHz and 23.2 mW at 67 MHz were achieved for the multi-stage PPRM architecture of SubBytes transformation and the AES encryption respectively. Compared to previous works, our AES implementations achieve good performance in term of power consumption.
Keywords :
CMOS integrated circuits; cryptography; AES design; AES encryption 128-bit; CMOS technology; MixColumns transformation; SubBytes transformation; advanced encryption standard; complementary metal oxide semiconductor; composite field arithmetic; frequency 10 MHz; frequency 67 MHz; low power consumption; multistage PPRM architecture; power 23.2 mW; power 24.92 muW; size 0.18 micron; CMOS integrated circuits; CMOS technology; Computer architecture; Encryption; Logic gates; Power demand; Standards;
Conference_Titel :
Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2012 7th International Conference on
Conference_Location :
Gammarth
Print_ISBN :
978-1-4673-1926-3
DOI :
10.1109/DTIS.2012.6232975
