Title :
Layout-based extraction of IC electrical behavior models
Author :
Wang, K. ; Rotella, F. ; Chen, T. ; Yang, D. ; Lee, A. ; Yu, Z. ; Knepper, R.W. ; Watt, J. ; Dutton, R.W.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
Behavior of IC structures is modeled using a heterogeneous set of tools and derived physical representations. A unified 3D information model is demonstrated with special emphasis on application of solid geometry modeling techniques. Examples used in this presentation include modeling of SRAM technology and interconnect structures that include packaging considerations as well. Issues of mixed level simulations are considered based on circuit and thermal constraints on IC structures.<>
Keywords :
SRAM chips; circuit CAD; circuit analysis computing; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; integrated circuit packaging; IC electrical behavior models; SRAM technology; interconnect structures; layout-based extraction; mixed level simulations; packaging considerations; solid geometry modeling techniques; unified 3D information model; Circuit simulation; Circuit synthesis; Computational Intelligence Society; Data mining; Information geometry; Integrated circuit layout; Integrated circuit modeling; Process design; Random access memory; Solid modeling;
Conference_Titel :
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2111-1
DOI :
10.1109/IEDM.1994.383429
