Abstract :
Error detecting and correcting code based memory design, self-checking design, VLSI-level retry architectures, perturbation hardened design, tools for evaluation of soft error rates, and other on-line testing techniques are becoming mandatory in order to achieve increasingly levels of soft-error robustness and push aggressively the limits of technological scaling. In the next few years, considerable efforts have to be concentrated on the development of such techniques and the related CAD tools
Keywords :
VLSI; built-in self test; circuit CAD; design for testability; error correction codes; error detection codes; integrated circuit reliability; integrated circuit testing; logic CAD; logic testing; radiation hardening (electronics); CAD tools; VLSI-level retry architectures; deep submicron scaling; design for soft-error robustness; error detecting and correcting codes; limits of technological scaling; memory design; on-line testing techniques; perturbation hardened design; self-checking design; single event upsets; soft error rates evaluation tools; soft-error-robust VLSI design; Circuits; Costs; Energy states; Error correction codes; Logic design; Noise reduction; Protection; Robustness; Testing; Very large scale integration;
