Abstract :
SOC (systems-on-a-chip) testing is still an ad hoc process to some degree. In attempting to solve the real problems of SOC testing, ideas are many and galore; even the technology seems to be getting there, but the devil is in the details: implementation, execution, reduction of tester-time, solving the problem of high-pin count ATE testing, detecting unmodeled defects (particularly of the AC-type), managing the size and complexity of the design, etc. The problems and their nature clearly point at BIST-type solutions. Nevertheless, it´s the up-front planning, integration and implementation of testability at the system/chip level that can provide the necessary solution. Practical solutions will need to be more than traditional BIST. An effective combination of test techniques, however dominated by BIST, seems to be the only viable and credible path to achieving a working solution. I believe that the final test responsibility lies with the chip and system designers: primarily because these are the ultimate end-product marketeers and sellers. Additionally, the solutions dictate design-phase planning and implementation as the only way to resolve the SOC test challenge
Keywords :
application specific integrated circuits; automatic testing; built-in self test; design for testability; integrated circuit testing; BIST-type solutions; design complexity; design-phase planning; high-pin count ATE testing; implementation problems; integration problems; multi-functional chips; system/chip level; systems-on-a-chip testing; test execution; test responsibility; testability; tester-time reduction; unmodeled defects detection; Analytical models; Built-in self-test; Costs; Electronic design automation and methodology; Forward contracts; Logic design; Packaging; Pins; System-on-a-chip; Testing;
