Title :
An EEPROM model for low power circuit design and simulation
Author :
Tat-Kwan Yu ; Higman, J. ; Cavins, C. ; Kuo-Tung Chang ; Orlowski, M.
Author_Institution :
Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA
Abstract :
A CAD EEPROM circuit model is essential to the design/optimization of low power non-volatile memory products. This paper presents a new FETMOS EEPROM circuit model that includes both Fowler-Nordheim and band-to-band tunneling. A DC model for FETMOS operation is derived and then extended to transient device operation. The model has been implemented into SPICE and applied to simulate the program/erase of a FETMOS bitcell and threshold voltage shifts under various bias conditions.<>
Keywords :
EPROM; MOS memory circuits; SPICE; circuit CAD; circuit analysis computing; equivalent circuits; integrated circuit design; integrated circuit modelling; transient analysis; tunnelling; CAD model; DC model; EEPROM model; FETMOS EEPROM; FETMOS bitcell program/erase; FN tunnelling; Fowler-Nordheim tunneling; MOS IC; MOSFET; SPICE; band-to-band tunneling; bias conditions; low power circuit design; nonvolatile memory; simulation; threshold voltage shifts; transient device operation; Capacitors; Circuit simulation; Circuit synthesis; EPROM; MOSFET circuits; Nonvolatile memory; Steady-state; Threshold voltage; Transient analysis; Tunneling;
Conference_Titel :
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2111-1
DOI :
10.1109/IEDM.1994.383441
