New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area

Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower poly-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout