Secondary protection scheme for CMOS I/O buffers and core circuits and their ESD sensitivity

A new CMOS I/O pad structure which is integrated into both input buffer and output pre-driver circuit separating both power line and ground line from output or pre-driver circuit for input buffer and the secondary protection circuit seems to solve an ESD protection problem, showing a good ESD results. The Vss/+ mode was the most sensitive at fixed total channel width and Vss/+ mode seems to have disabled/enabled transistor dependency. CMOS I/O ESD sensitivity is proportional to the channel width and shorter channel length shows better ESD results