A memristor-based LUT for FPGAs

This paper presents a memristor-based Look-Up Table (LUT) for FPGAs. The proposed memory utilizes memristors as storage elements and NMOS transistors for selection. New WRITE and READ operations are proposed; the proposed LUT requires no additional circuit to handle the WRITE 1 (0) operation for both the word and bit lines. Also, it requires a RESTORE pulse only for the READ 0 operation. The WRITE operation of the proposed method requires three power lines (+Vdd, -Vdd and Gnd) and a RESTORE pulse only for the READ 0 operation, thus accomplishing savings of 25% for both the number of power lines and READ time when compared to previous methods. The proposed LUT is simulated using LTSPICE and extensive simulation results are presented with respect to different operational features, such as normalized state parameter of the memristance, pulse width, LUT size and MOSFET feature size. These results show that the proposed scheme offers superior performance compared with other existing memristor-based schemes found in the technical literature for FPGAs.