DocumentCode :
2528316
Title :
Bandwidth-aware test compression logic for SoC designs
Author :
Janicki, Jakub ; Tyszer, Jerzy ; Mrugalski, Grzegorz ; Rajski, Janusz
Author_Institution :
Poznan Univ. of Technol., Poznan, Poland
fYear :
2012
fDate :
28-31 May 2012
Firstpage :
1
Lastpage :
6
Abstract :
This paper presents novel methods of enhancing test compression solutions for SoC designs. The ability of the proposed schemes to improve the encoding efficiency, test compression, and test time is accomplished by either appropriate selecting or laying out ATE channel injectors within EDT-based decompressors. The efficacy of new techniques with respect to test bandwidth management is demonstrated by running experiments on several industrial SoC designs and is reported herein.
Keywords :
bandwidth compression; logic circuits; system-on-chip; ATE channel injector; EDT-based compressor; SoC design; bandwidth management; bandwidth-aware test compression logic; encoding efficiency; test compression; Bandwidth; Encoding; Multicore processing; Phase shifters; Ring generators; Switches; System-on-a-chip; channel bandwidth management; embedded deterministic test; scan-based designs; test data compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ETS), 2012 17th IEEE European
Conference_Location :
Annecy
Print_ISBN :
978-1-4673-0696-6
Electronic_ISBN :
978-1-4673-0695-9
Type :
conf
DOI :
10.1109/ETS.2012.6233003
Filename :
6233003
Link To Document :
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