ESD effects on power supply clamps [CMOS ICs]

Author

Yeoh, Teong San

Author_Institution

Intel Technol. Sdn. Bhd., Penang, Malaysia

fYear

1997

fDate

21-25 Jul 1997

Firstpage

121

Lastpage

124

Abstract

Electrostatic discharge (ESD) damage is a common failure mechanism that is seen on CMOS integrated circuit devices. Due to the ever increasing shrinkage in transistor geometries, prevention of ESD damage will become increasingly important. This paper discusses the various device level ESD in the form of power supply clamps. There are numerous power supply clamps that are currently available such as the grounded gate, thick field oxide (TFO), diode string and cantilever diode structures. Selection of the right ESD power supply clamp is essential from the aspects of their limitations, weaknesses, silicon space and effectiveness to ensure robustness during to ESD stresses on devices

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; limiters; protection; CMOS IC; ESD protection devices; ESD stress robustness; cantilever diode structures; device level ESD effects; diode string structures; electrostatic discharge damage; failure mechanism; grounded gate structure; integrated circuit devices; power supply clamps; thick field oxide structure; CMOS integrated circuits; Clamps; Diodes; Electrostatic discharge; Failure analysis; Geometry; Power supplies; Robustness; Silicon; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical & Failure Analysis of Integrated Circuits, 1997., Proceedings of the 1997 6th International Symposium on

Print_ISBN

0-7803-3985-1

Type

conf

DOI

10.1109/IPFA.1997.638156

Filename

638156