DocumentCode :
2528407
Title :
BIST design for analog cell matching
Author :
Duarte, Cândido ; Cavadas, Henrique ; Coke, Pedro ; Malheiro, Luís ; Tavares, Vítor Grade ; De Oliveira, Pedro Guedes
Author_Institution :
INESC TEC (formerly INESC Porto), Univ. of Porto, Porto, Portugal
fYear :
2012
fDate :
28-31 May 2012
Firstpage :
1
Lastpage :
6
Abstract :
This work addresses a built-in self-test methodology for circuit cell identification under specific matching conditions. The proposed technique is applied to the CMOS realization of a reduced-KII network, which is a system model of the biological olfactory cortex. This model behaves as an associative memory, a useful tool for information and adaptive processes. Based on a mixed-signal approach, the test strategy makes proper use of the circuits comprising the network structure, and provides self reconfiguration as well. Both testing procedures and design of essential building blocks are described in this paper. Simulation results are presented for a reduced-KII network comprising 128-cells, sequentially tested for matching in terms of offsets and their dynamic performances.
Keywords :
CMOS integrated circuits; analogue circuits; built-in self test; BIST design; CMOS realization; adaptive process; analog cell matching; associative memory; biological olfactory cortex; built-in self-test methodology; circuit cell identification; information process; mixed-signal approach; network structure; reduced-KII network; self reconfiguration; specific matching condition; Built-in self-test; Clocks; Integrated circuit interconnections; Multiplexing; Probability density function; Silicon; adaptive processes; design for testability; matching algorithms; mixed-signal BIST; neuromorphic circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ETS), 2012 17th IEEE European
Conference_Location :
Annecy
Print_ISBN :
978-1-4673-0696-6
Electronic_ISBN :
978-1-4673-0695-9
Type :
conf
DOI :
10.1109/ETS.2012.6233008
Filename :
6233008
Link To Document :
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