Title :
Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs
Author :
Laraba, Asma ; Stratigopoulos, Haralampos-G ; Mir, Salvador ; Naudet, Hervé ; Forel, Christophe
Author_Institution :
TIMA Lab., UJF, Grenoble, France
Abstract :
The reduced code linearity test technique for pipeline ADCs consists in measuring some judiciously selected codes which contain the information about the linearity of the converter as opposed to the standard histogram technique that considers indiscriminately all codes. This technique dramatically reduces the static test time for pipeline ADCs. In this paper, we identify some limitations in the existing version of the technique and we provide solutions to enhance its accuracy. The enhanced technique is applied to a 12-bit 2.5-bit/stage pipeline ADC.
Keywords :
analogue-digital conversion; code linearity test technique; converter; multi-bit pipeline ADC; stage pipeline ADC; standard histogram technique; static test time; Computer architecture; Digital circuits; Dynamic range; Histograms; Linearity; Pipelines; Transfer functions;
Conference_Titel :
Test Symposium (ETS), 2012 17th IEEE European
Conference_Location :
Annecy
Print_ISBN :
978-1-4673-0696-6
Electronic_ISBN :
978-1-4673-0695-9
DOI :
10.1109/ETS.2012.6233009
