Title :
Digit-serial/parallel multipliers with improved throughput and latency
Author :
Karlsson, Magnus ; Vesterbacka, Mark
Author_Institution :
Dept. of Technol., Kalmar Univ.
Abstract :
Digit-serial/parallel multipliers with improved throughput and latency are presented. The multipliers are based on unfolded bit-serial/parallel multipliers. The unfolding yields long critical paths that are reduced by splitting the multiplication as a sum of partial multiplications. Using a sum of two partial multiplications yields an increased throughput with between 50 and 120 percent and the latency is reduced with up to 50 percent, compared with the basic digit-serial/parallel multiplier based on unfolding
Keywords :
digital arithmetic; multiplying circuits; critical path; digit-serial-parallel multipliers; partial multiplication; unfolded bit-serial-parallel multipliers; Algorithm design and analysis; Arithmetic; Clocks; Delay; Digital filters; Digital signal processing; Pipeline processing; Registers; Tellurium; Throughput;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692507
