A study of design/process dependence of 0.25 /spl mu/m gate length CMOS

We investigate the design/process dependence of a 0.25 /spl mu/m gate length CMOS technology and evaluate performance (including I/sub drive/ vs. I/sub off/, I/sub drive/ at the onset of subthreshold 2/sup nd/ slope, inverse-short-channel effect) and reliability (channel hot electron lifetime, gate-induced drain leakage, and ESD related thermal, or 2/sup nd/ breakdown). Increased nMOS I/sub drive/ before onset of subthreshold 2/sup nd/ slope (resulting from sub-surface S/D punch-through) is realized with increased As S/D anneal temperature and is correlated with reduced inverse-short-channel effect (i-SCE: measure of increase in V/sub T/ with decreasing L/sub gate/). Improved nMOS I/sub drive/ vs. I/sub off/ is additionally achieved (at same R/sub SD/) using S/D with As only compared to P LDD and is correlated with reduced sub-surface punch-through. Use of RTA annealing to 1000/spl deg/C reduces i-SCE for non-LDD nMOS as well as increasing pMOS C/sub invC/sub ox/ to /spl ges/90% at t/sub ox/=50 /spl Aring/. (comparable to nMOSFET). nMOS ESD reliability (as measured by I/sub t2/: drain current at ESD related 2/sup nd/ breakdown) is increased with optimum S/D anneal and with As only S/D. nMOS pocket implant reduces V/sub T/ rolloff and maintains hot carrier reliability and I/sub t2/ while marginally increasing C/sub j/. Use of nMOS pocket implant and pMOS super-steep retrograde channel implant improve the V/sub T/ rolloff but do not show significant improvement in I/sub drive/ vs. I/sub off/. A design/process has been implemented which results in a high performance CMOS technology consistent with industry trend as measured using a figure-of-merit metric.<>