DocumentCode
2528712
Title
Low power binary addition using carry increment adders
Author
Grad, Johannes ; Stine, James E.
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL
fYear
2006
fDate
21-24 May 2006
Lastpage
20
Abstract
Sparse prefix tree adders like carry-select adders and carry-increment adders are commonly used in the implementation of high-speed parallel adders. This paper presents a novel Ling carry-increment adder, which further reduces the area and power consumption as compared to a conventional carry-increment adder. The proposed algorithm utilizes Ling pseudo-carries in both the prefix tree and the output sum blocks. The algorithm is verified with the implementation of two 64-bit adders using the conventional carry-increment and the proposed Ling carry-increment algorithms. An 8-bit sum block using the proposed algorithm uses 7% fewer devices and consumes 16% less energy, while the complete adder uses 8% fewer transistors and consumes 7% less energy
Keywords
adders; carry logic; low-power electronics; 64 bit; 8 bit; Ling carry-increment adder; Ling pseudocarries; binary addition; carry-select adders; high-speed parallel adders; sparse prefix tree adders; Added delay; Adders; Algorithm design and analysis; Digital systems; Energy consumption; Logic circuits; Power engineering and energy; Power generation; Propagation delay; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1692511
Filename
1692511
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