Title :
A dual-bit split-gate EEPROM (DSG) cell in contactless array for single-Vcc high density flash memories
Author :
Ma, Y. ; Pang, C.S. ; Chang, K.T. ; Tsao, S.C. ; Frayer, J.E. ; Taehyoung Kim ; Kwanghyun Jo ; Jeoungwoo Kim ; Ilhyun Choi ; Heungsup Park
Author_Institution :
Bright Microelectronic Inc., Santa Clara, CA, USA
Abstract :
A new source-side injection Dual-bit Split-Gate (DSG) flash EEPROM cell is designed and characterized. With a 0.6 /spl mu/m process, the cell-size of 1.95 /spl mu/m/sup /spl and//2 per bit in a contactless array is achieved. With a shared select-gate, the cell consists of three directly jointed channels. Taking advantage of the split-gate structure, the threshold voltage of the floating-gate transistor is allowed to move from enhancement-mode to depletion-mode between write and erase operations. Only moderate voltages (less than 10 V) are required the for the cell operations, which relax the high-voltage device requirements on peripheral circuitry and thus simplify the process with less masking steps. With on-chip charge pumps, this cell is suitable for very high density and low power mass-storage applications with single-Vcc power supply.<>
Keywords :
EPROM; cellular arrays; integrated memory circuits; 0.6 micron; 10 V; EEPROM cell; contactless array architecture; depletion-mode; dual-bit split-gate; enhancement-mode; erase operation; floating-gate transistor; high density flash memories; low power mass-storage applications; onchip charge pumps; shared select-gate; single-Vcc power supply; source-side injection; threshold voltage; write operation; Character generation; EPROM; Flash memory; Nonvolatile memory; Power supplies; Secondary generated hot electron injection; Split gate flash memory cells; Switches; Tunneling; Voltage;
Conference_Titel :
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2111-1
DOI :
10.1109/IEDM.1994.383467
