Title :
Defect analysis in power mode control logic of low-power SRAMs
Author :
Zordan, L.B. ; Bosio, A. ; Dilillo, L. ; Girard, P. ; Todri, A. ; Virazel, A. ; Badereddine, N.
Author_Institution :
LIRMM, Univ. Montpellier II, Montpellier, France
Abstract :
Summary form only given. Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is applied in SRAMs using power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This paper provides a detailed analysis based on electrical simulations to describe the impacts of resistive-open defects on the power mode control logic, which generates control signals of power switches.
Keywords :
SRAM chips; low-power electronics; power control; switches; voltage control; I-O logic; decoder; electrical simulation; low-power SRAM; memory block; power gating mechanism; power mode control logic; power switch; resistive-open defect analysis; signal control generation; static power consumption reduction; supply voltage control; Arrays; Control systems; Power demand; Random access memory; System-on-a-chip; Transistors; Voltage control; SRAM; failure analysis; low-power design; memory test; power mode control logic; power switch;
Conference_Titel :
Test Symposium (ETS), 2012 17th IEEE European
Conference_Location :
Annecy
Print_ISBN :
978-1-4673-0696-6
Electronic_ISBN :
978-1-4673-0695-9
DOI :
10.1109/ETS.2012.6233033
