2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop

Author

Shin, Sangho ; Lee, Kwyro ; Kang, Sung-Mo

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon

fYear

2006

fDate

21-24 May 2006

Abstract

This paper describes a radio architecture with fast analog frequency offset cancellation loop which is based on a SigmaDelta fractional-N frequency synthesizer and a frequency offset detector. The offset detector is composed of a frequency/phase detector (PFD) and a new non-uniform resolution time-to-digital converter (TDC). By adopting the weighted delay-length for the TDC, only 60-DFFs are used to generate digitized timing difference of 250ns with a minimum resolution of 1ns. For the 2.4GHz ZigBee transceiver with 4MHz IF, designed for 0.18mum CMOS process, the frequency offset cancellation time takes about 30mus under the PLL loop-bandwidth of 100 kHz

Keywords

CMOS integrated circuits; frequency synthesizers; phase detectors; phase locked loops; transceivers; 0.18 micron; 100 kHz; 2.4 GHz; 250 ns; 4 MHz; CMOS process; PFD; PLL; TDC; ZigBee radio architecture; ZigBee transceiver; analog frequency offset cancellation loop; fractional-N frequency synthesizer; frequency offset detector; frequency-phase detector; time-to-digital converter; CMOS process; Delay; Frequency conversion; Frequency locked loops; Frequency synthesizers; Phase detection; Phase frequency detector; Timing; Transceivers; ZigBee;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692531

Filename

1692531