Online detection and recovery of transient errors in front-end structures of microprocessors

Summary form only given. In this paper, we propose schemes for protecting the front-end logic of present-day superscalar processors. This logic is comprised of several structures like Rename Table, Issue Queue (IQ) and Re-order buffers (ROB) which contain critical information about instructions moving through the pipeline. As the instructions reside in these structures for multiple cycles, the Architecture Vulnerability Factor (AVF) of these structures is significantly high. The proposed schemes look at the lifetime of instructions in various pipeline structures, utilize the inherent redundancy present in the front-end logic of the pipeline and increase it to a minimal level, in order to detect and recover from transient errors.