A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a simple memory control scheme

A simple addressing scheme for pipeline MDC shared-memory architecture with mixed-radix algorithm is proposed. It can provide a simple control circuit for memory addressing generation, and the mixed-radix butterfly sequence can be automatically generated by way of simple counter. In addition, for the N-point FFT processor, only N/8 coefficients should be stored in the VLSI implementation, therefore, the ROM size and the FFT processor area are reduced. According to the simple control scheme and small memory size, the low-power VLSI architecture can be achieved. Furthermore, the architecture with the mixed-radix algorithm also enhances the speed in performing large-point FFT computations compared with the existing shared-memory architectures. Based on this architecture, not only radix-2³ butterfly is adopted to achieve the requirement of high throughput, but also radix-2 ² or radix-2 butterfly is utilized to allow all of FFT calculation for N=2ⁿ. An VLSI architecture of 8192-point FFT processor with only power consumption of 890muW is also implemented to demonstrate the proposed method