DocumentCode
2529496
Title
A VLSI array processor accelerator for k-NN classification
Author
Ferrari, A. ; Borgatti, M. ; Guerrieri, R.
Author_Institution
DEIS, Bologna Univ., Italy
Volume
4
fYear
1996
fDate
25-29 Aug 1996
Firstpage
723
Abstract
This paper describes a VLSI array processor system that has been designed and built for classification problems based on the k-nearest neighbors approach. This architecture is suitable for different pattern recognition applications and is scalable to reduce the computation time. A prototype board with two processors has been built and a software driver has been written showing a speed up of 30 times over a software algorithm running on a Sun SPARC20 workstation
Keywords
VLSI; optical character recognition; parallel architectures; Sun SPARC20 workstation; VLSI array processor accelerator; k-nearest neighbors; optical character recognition; parallel architecture; pattern classification; pattern recognition; software driver; Character recognition; Laser radar; Nearest neighbor searches; Neural networks; Performance evaluation; Semiconductor device measurement; Shape measurement; Sun; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Pattern Recognition, 1996., Proceedings of the 13th International Conference on
Conference_Location
Vienna
ISSN
1051-4651
Print_ISBN
0-8186-7282-X
Type
conf
DOI
10.1109/ICPR.1996.547659
Filename
547659
Link To Document