Multi-threshold CMOS design for low power digital circuits

Multi-threshold CMOS (MTCMOS) power gating is a design technique in which a power gating transistor is connected between the logic transistors and either power or ground, thus creating a virtual supply rail or virtual ground rail, respectively. Power gating transistor sizing, transition (sleep mode to active mode) current, short circuit current and transition time are design issues for power gating design. The use of power gating design results in the delay overhead in the active mode. If both nMOS and pMOS sleep transistor are used in power gating, delay overhead will increase. This paper proposes the design methodology for reducing the delay of the logic circuits during active mode. This methodology limits the maximum value of transition current to a specified value and eliminates short circuit current. Experiment results show 16.83% reduction in the delay.