DocumentCode
2529865
Title
Register Traffic Analysis For Streamlining Inter-operation Communication In Fine-grain Parallel Processors
Author
Franklin, Manoj ; Sohi, Gurindar S.
Author_Institution
University of Wisconsin-Madison
fYear
1992
fDate
1-4 Dec 1992
Firstpage
236
Lastpage
245
Keywords
Bandwidth; Computational modeling; Computer aided instruction; Computer architecture; Concurrent computing; Instruction sets; Modems; Process design; Registers; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microarchitecture, 1992. MICRO 25., Proceedings of the 25th Annual International Symposium on
Print_ISBN
0-8186-3175-9
Type
conf
DOI
10.1109/MICRO.1992.697025
Filename
697025
Link To Document