Title :
A high-speed Reed-Solomon decoder for correction of both errors and erasures
Author :
Cai, Zhaohui ; Hao, Jianzhong ; Sun, Sumei ; Chin, Francois Poshin
Author_Institution :
Inst. for Infocomm Res., Singapore
Abstract :
This paper presents the design of a (n,k) Reed-Solomon decoder for both errors and erasures. The key-equation solver is based on Sarwate´s reformulated inversionless Berlekamp-Massey algorithm. The decoder has been implemented on FPGA and the maximum clock frequency can be 150 MHz for a (255, 239) code on a Xilinx Virtex-II device
Keywords :
Reed-Solomon codes; clocks; decoding; error correction codes; field programmable gate arrays; high-speed techniques; 150 MHz; Berlekamp-Massey algorithm; FPGA implementation; Reed-Solomon decoder; Sarwate reformulation; Xilinx Virtex-II device; erasure correction; error correction; high-speed decoder; key-equation solver; Clocks; Equations; Error correction; Error correction codes; Field programmable gate arrays; Frequency; Iterative decoding; Polynomials; Reed-Solomon codes; Sun;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692577
