A low energy VLSI design of random block interleaver for 3GPP turbo decoding

Author

Ahmed, Imran ; Arslan, Tughrul

Author_Institution

Sch. of Electron. & Eng., Edinburgh Univ.

fYear

2006

fDate

21-24 May 2006

Lastpage

288

Abstract

In this paper hardware architecture for internal random block interleaver compliant with the 3rd Generation Partnership Project (3GPP) turbo decoding is described. The complexity of this algorithm results in other implementations using large memories as address tables. In this implementation real time address computation avoids the use of pre-computed address storage. This greatly reduces the load on the processor and gives significant improvements in area and power. ASIC synthesis results on 0.18 mum CMOS UMC technology demonstrate the efficiency of the proposed VLSI interleaver architecture

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; computational complexity; integrated circuit design; interleaved codes; turbo codes; 0.18 micron; 3GPP turbo decoding; ASIC synthesis; CMOS technology; VLSI design; address computation; address storage; address tables; random block interleaver; CMOS technology; Concatenated codes; Convolutional codes; Delay; Hardware; Interleaved codes; Iterative decoding; Random access memory; Tellurium; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692578

Filename

1692578