VLSI architecture for 4 /spl times/ 4 16-QAM V-BLAST decoder

This paper presents the VLSI architecture for the V-BLAST detection for a 4 times 4 16-QAM MIMO wireless communication systems based on the QR factorization technique. We present the design and optimization of the pre decoder block based on the CORDIC rotator processors. We also present the architecture of the back substitution symbol interference cancellation (SIC) block that eliminates the need for division and multiplication, thereby substantially, reducing the hardware cost, without compromising the numerical stability. The proposed VLSI architecture is implemented on an Altera Stratix FPGA. A detection throughput of 149 Mb/s is achieved on this platform. This paper also investigates the use of a parallel decoding scheme to improve the BER performance