Title :
Lossless data compression core design for integrated space data and communication system-on-chip
Author_Institution :
NASA Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA
Abstract :
A CCSDS-compliant lossless data compressor core for space data and communication system-on-chip designs has been developed to meet the increasing strong demands on high-bandwidth high-speed space data systems. This data compressor core is based on CCSDS lossless data compression standard and designed with space-qualified 150-nm CMOS technology. It occupies a compact chip area of about 700mum times 700 mum. The total power dissipation is 0.2 watts at a throughput rate of 66 Msamples/sec. This compressor core meets low-power, high-throughput, and user-transparent requirements and will be one of valuable silicon intellectual properties for developing next generation high-performance system-on-chip based space data and communication systems
Keywords :
CMOS integrated circuits; avionics; data compression; system-on-chip; 0.2 W; 150 nm; 700 micron; CMOS technology; Consultative Committee for Space Systems; communication system-on-chip; data compression core; integrated space data; Aerospace electronics; Algorithm design and analysis; CMOS technology; Data compression; Hardware; NASA; Space missions; Space technology; System-on-a-chip; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692581
