Low power compact design of ARIA block cipher

Author

Park, Jinsub ; Kim, Young-Dae ; Yang, Sangwoon ; You, Younggap

Author_Institution

Sch. of Electr. & Comput. Eng., Chungbuk Nat. Univ., Cheongju

fYear

2006

fDate

21-24 May 2006

Lastpage

316

Abstract

This paper presents a 32-bit hardware architecture reduced from the original 128-bit ARIA cryptographic algorithm. The hardware design in this paper is a low-power and compact version of ARIA for mobile environment. We use four S-boxes and modify a diffusion function and its data-path to reduce a hardware size. The proposed 32-bit ARIA needs 63 clock cycles to generate initial values for a round key and 356 clock cycles to encrypt a single message packet. The 32-bit ARIA has 13,893 gates. It is 62.5 % smaller than the original 128-bit ARIA. The power consumption is 61.46mW, 9.7% of the 128-bit version at 71MHz

Keywords

cryptography; low-power electronics; microprocessor chips; mobile handsets; 128 bit; 32 bit; 61.46 mW; 71 MHz; ARIA cryptographic algorithm; data path; diffusion function; hardware design; low power compact design; mobile environment; Algorithm design and analysis; Clocks; Computer architecture; Cryptography; Data security; Energy consumption; Hardware; National security; Power engineering and energy; Power engineering computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692585

Filename

1692585