Channel based routing in channel-less circuits

This work explores an alternative model for area routing, which employs horizontally aligned terminals in each row of cells, providing channel-like routing areas. We have developed a two-layer router that decomposes the routing problem into smaller pieces and takes advantage of the low time complexity that channel routing has in order to provide fast and convergent area routing for channel-less cell-based circuits. Comparing to maze routing, our toll shows an average increase in wire-length of only 0.6%, and area increase of 7.2%, due to the insertion of spaces. But results show that it achieves 100% routing in almost linear time for our test circuits. This is the main contribution of this kind of simultaneous, variable-die approach when compared to traditional fixed-die methodologies. Convergence and short CPU times are crucial in many IC designs, mainly when time-to-market is a tighter constraint. But they can contribute also in any methodology helping to meet other design constraints by not getting stuck in non-convergent loops