Title :
A 3.6 mu m/sup 2/ memory cell structure for 16 Mb EPROMs
Author :
Hisamune, Y.S. ; Kodama, N. ; Saitoh, K. ; Okazawa, T. ; Yamanaka, H. ; Kikuchi, M.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
A 2.0- mu m*1.8- mu m floating-gate-type memory cell, based on a 0.6- mu m design rule, has been developed for 16-Mb EPROMs (electrically programmable ROMs). The cell size is about 40% that of the smallest 4-Mb EPROM cell reported so far. The cell also features a fast programming time of 10 mu s. The process technologies used are trench-self-aligned isolation refilled with BPSG, oxide-nitride-oxide interpoly dielectrics and bit-line contact with silicide pad and selective CVD (chemical vapor deposited) tungsten.<>
Keywords :
EPROM; MOS integrated circuits; integrated memory circuits; 0.6 micron; 10 mus; 16 Mbit; B2O3-P2O5-SiO2; BPSG refill; EPROM cell; bit-line contact; chemical vapour deposited W; electrically programmable ROMs; floating-gate-type; memory cell structure; oxide-nitride-oxide interpoly dielectrics; process technologies; programming time; selective CVD; silicide pad; trench-self-aligned isolation; Chemical processes; Chemical technology; Chemical vapor deposition; Contacts; Dielectrics; EPROM; Isolation technology; Nonvolatile memory; Read only memory; Silicides;
Conference_Titel :
Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1989.74348
