A single chip image sensor embedded smooth spatial filter with A/D conversion

Author

Tsai, Chia-Chun ; Chou, Huang-Chi ; Lee, Trong-Yen ; Hsiao, Rong-Shue

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nanhua Univ., Chiayi

fYear

2006

fDate

21-24 May 2006

Abstract

The paper presents a current-mode CMOS image sensor embedded smooth spatial filter algorithm. The sensor includes a 66times66 pixel array with an on-chip 6-bit analog-to-digital converter that can identify the output value of pixels in gray level resolution. The last row of pixel cells (1times66) based on the double sampling is used for reducing fixed pattern noise (FPN). Processing circuits are dedicated for the spatial filter algorithm and support reusability to increase the image processing speed and to reduce the design complexity and chip area. The sensor chip has been designed and implemented in TSMC 0.35mum 2P4M CMOS mixed-mode process. Each pixel occupies a area of 15.8mumtimes10.6mum with a fill factor of 37.2%. The power consumption is 35.15mW when the sensor operates at 175 frames/second

Keywords

CMOS image sensors; analogue-digital conversion; current-mode circuits; integrated circuit design; mixed analogue-digital integrated circuits; spatial filters; 0.35 micron; 10.6 micron; 15.8 micron; 35.15 mW; 6 bit; A/D conversion; CMOS mixed-mode process; analog-to-digital converter; current-mode CMOS image sensor; fixed pattern noise; gray level resolution; image processing; pixel cells; processing circuits; sensor chip; smooth spatial filter algorithm; Analog-digital conversion; CMOS image sensors; Circuit noise; Image converters; Image sampling; Image sensors; Noise reduction; Sensor arrays; Spatial filters; Spatial resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692613

Filename

1692613