A high performance CMOS process for submicron 16 Mb EPROM

Author

Bergemont, A. ; Deleonibus, S. ; Guegan, Guillaume ; Guillaumot, B. ; Laurens, M. ; Martin, F.

Author_Institution

SGS Thomson, Grenoble, France

fYear

1989

fDate

3-6 Dec. 1989

Firstpage

591

Lastpage

594

Abstract

A high-performance and reliable 0.6 mu m CMOS process has been developed for the fabrication of next-generation 16-Mb density high-speed electrically programmable ROMs (EPROMs). The key process technologies are: (a) less than 0.2- mu m bird´s beak isolation; (b) high-performance n/p channel LDD (lightly doped drain) transistors; (c) thin reliable interpoly dielectrics; (d) cold end processing using RTA (rapid thermal annealing) for both glass reflow and n/sup +/,p/sup +/ junction activation; and (e) less than 4.5- mu m/sup 2/ cell area (for practical die size) with fast writing speed, sufficient read current, and soft write endurance.<>

Keywords

CMOS integrated circuits; EPROM; integrated circuit technology; integrated memory circuits; 0.6 micron; 16 Mbit; CMOS process; EPROM; LDD transistors; RTA; bird´s beak isolation; cold end processing; electrically programmable; fabrication; glass reflow; high speed EPROM; lightly doped drain; n/sup +/,p/sup +/ junction activation; process technologies; rapid thermal annealing; reliable interpoly dielectrics; soft write endurance; submicron memory features; CMOS process; CMOS technology; Dielectrics; EPROM; Fabrication; Isolation technology; Rapid thermal annealing; Rapid thermal processing; Read only memory; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1989.74350

Filename

74350