Artificial intelligence approach to test vector reordering for dynamic power reduction during VLSI testing

As the feature size is scaled down with process technology advancement, power minimization has become a serious problem for the designers as well as the test engineers. Test vector reordering for dynamic power minimization during combinational circuit testing is a sub-problem of the general goal of low power testing. In this paper we have proposed an AI-based approach to order the test vectors in an optimal manner to minimize switching activity during testing. Empirically, the proposed algorithm yields on an average of about 22% reduction in switching activity over that given by a standard ATPG tool Synopsis TetraMax, which is also more than the reduction after applying existing Chained Lin-Kernighan heuristic.