Minimization of energy dissipation in glitch free and cascadable adiabatic logic circuits

The energy dissipation in the logic circuits can be reduced by using adiabatic techniques. In this paper, we describe a technique for further reduction in energy dissipation in glitch free and cascadable adiabatic logic (GFCAL) circuits by using two complementary supply waveforms and single input signal. Measurements of energy drawn, energy recovered and dissipated have been carried out through simulation. The reduction in energy dissipation in the inverter proposed is about 65 percent compared to that of standard CMOS, up to 1000 MHZ.