Modelling the hot-carrier induced degradation in the subthreshold characteristics of submicrometer LDD PMOSFETs

Author

Lou, C.L. ; Qin, W.H. ; Chim, W.K. ; Chan, D.S.H.

Author_Institution

Fac. of Eng., Nat. Univ. of Singapore, Singapore

fYear

1997

fDate

21-25 Jul 1997

Firstpage

127

Lastpage

132

Abstract

Hot-carrier injection is observed to increasingly degrade the subthreshold characteristics with the scaling of LDD PMOSFETs. A physical subthreshold current model is applied to the fresh and hot-carrier stressed submicrometer channel length devices. The generated interface traps and channel length reduction are subsequently extracted. An empirical model is developed to characterize the degradation parameters as a function of stress time and channel length. With the use of this model, we can determine the degradation parameters and hence predict the minimum allowable channel length (for a certain percentage of degradation and lifetime) that is applicable for a specific technology

Keywords

CMOS integrated circuits; MOSFET; electron traps; hole traps; hot carriers; integrated circuit modelling; integrated circuit reliability; interface states; semiconductor device models; semiconductor device reliability; PMOSFET scaling; channel length reduction; degradation parameters; empirical model; hot-carrier induced degradation; hot-carrier injection; interface traps; p-channel MOSFET; physical subthreshold current model; stress time; submicron LDD PMOSFET; submicron channel length devices; subthreshold characteristics; Degradation; Electrons; Failure analysis; Hot carriers; Integrated circuit reliability; MOSFETs; Predictive models; Stress; Subthreshold current; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical & Failure Analysis of Integrated Circuits, 1997., Proceedings of the 1997 6th International Symposium on

Print_ISBN

0-7803-3985-1

Type

conf

DOI

10.1109/IPFA.1997.638174

Filename

638174