Title :
A digital signal processing based bit synchronizer and novel hardware efficient lock detector circuit for bi-phase data for Chandrayaan-1 mission
Author :
Sharma, Satish ; Kulkarni, Sunil ; Pujari, Vijaykumar ; Lakshimnarsimhan, P.
Abstract :
The paper presents hardware efficient design of digital signal processing (DSP) based bit synchronizer and lock detector circuit for bi-phase data. The system is developed for one of the payload of Chandrayaan-I mission, and tested for its performance. Apart from the implementation, paper describes the mathematical modeling of bit synchronizer. The whole design is accommodated in a single Actel-1280 FPGA. A comparison has been carried out between the developed lock detector circuit and the traditional I2 - Q2 lock detector and results are presented here. Paper also highlights the programmable nature of the design and methods to reduce the hardware requirement.
Keywords :
aerospace instrumentation; artificial satellites; detector circuits; signal processing equipment; synchronisation; Actel-1280 FPGA; Chandrayaan-1 mission; I2 - Q2 lock detector; biphase data; bit synchronizer; digital signal processing; field programmable gate arrays; novel hardware efficient lock detector circuit; Circuit testing; Design methodology; Detectors; Digital signal processing; Field programmable gate arrays; Hardware; Mathematical model; Payloads; Signal design; System testing; Field programmable gate arrays; Satellite communication; Signal processing; Synchronization;
Conference_Titel :
TENCON 2008 - 2008 IEEE Region 10 Conference
Conference_Location :
Hyderabad
Print_ISBN :
978-1-4244-2408-5
Electronic_ISBN :
978-1-4244-2409-2
DOI :
10.1109/TENCON.2008.4766754