New scan method and pipeline architecture for VLSI implementation of separable 2-D FIR filters without transposition

In this paper, we propose a data-access scheme for transposition-free implementation of separable 2-D finite impulse response (FIR) filters for finite input matrix. The functionality of 2-D FIR filter based on the proposed data-access technique has been validated through MATLAB simulation. A pipelined architecture is derived further for hardware-efficient high-throughput implementation of this filter. The proposed design is found to have very low hardware-complexity compared with the best of the existing separable designs. Besides, it performs the filtering operation at a high rate due to its small clock period. Most importantly, the proposed one does not involve any line buffer for storing the intermediate results, so that significant amount of chip-area and power-consumption can be saved if the 2-D FIR filters are implemented using the proposed scheme.