DocumentCode
2531094
Title
Optimum wire tapering for minimum power dissipation in RLC interconnects
Author
El-Moursy, Magdy A. ; Friedman, Eby G.
Author_Institution
Dept. of Electr. & Comput. Eng., Rochester Univ., NY
fYear
2006
fDate
21-24 May 2006
Abstract
The optimum tapered structure for RLC interconnect to minimize transient power dissipation is determined. Wire tapering can reduce the power dissipated by a circuit by up to 72% as compared to uniform wire sizing. An analytic solution to determine the optimum tapered structure exhibits an error of less than 2% as compared to SPICE
Keywords
RLC circuits; integrated circuit design; integrated circuit interconnections; RLC interconnects; SPICE; optimum wire tapering; power dissipation; wire sizing; Contracts; Driver circuits; Integrated circuit interconnections; Inverters; Power dissipation; Propagation delay; RLC circuits; SPICE; Shape; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1692628
Filename
1692628
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