• DocumentCode
    2531113
  • Title

    Automatic analog fault simulation

  • Author

    Spence, H.

  • Author_Institution
    Southwest Res. Inst., San Antonio, TX
  • fYear
    1996
  • fDate
    16-19 Sep 1996
  • Firstpage
    17
  • Lastpage
    22
  • Abstract
    This paper presents an approach for using analog simulation together with artificial neural networks as a tool in the development of a test strategy. Relationships between circuit components and node states provided by simulation are used to create relationship matrices for a neural network. This approach provides a guide to diagnosing circuits by developing inferences about circuit component problems. The approach presented in this paper is a component of an automated test program generation (ATPG) concept. Problems associated with this approach are identified and defined. An industry accepted simulation engine generates data for operational circuit behavior. The simulation engine uses a netlist consisting of a to-from list, model definitions and an input description. Failures are simulated by one of two methods: (1) modifying circuit netlist, (2) modifying components. The circuit netlist is modified by adding opens and shorts to circuit nodes. The component models are modified by changing the component parameters within the component library. Simulation faults are chosen by the test program developer. Measures of component and node deviations from normal are used in the development of neural network matrices. An example analog circuit demonstrates the approach and typical results. This work may lead to development of a test strategy engine for automated analog test program development
  • Keywords
    SPICE; analogue simulation; automatic test software; circuit analysis computing; diagnostic expert systems; fault diagnosis; neural nets; ATPG; artificial neural networks; automated analog test program development; automated test program generation; automatic analog fault simulation; circuit netlist; component models; model definition; node states; opens; operational circuit; relationship matrices; shorts; simulation engine; simulation faults; test strategy; Artificial neural networks; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Engines; Industrial relations; Libraries; Neural networks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    AUTOTESTCON '96, Test Technology and Commercialization. Conference Record
  • Conference_Location
    Dayton, OH
  • ISSN
    1088-7725
  • Print_ISBN
    0-7803-3379-9
  • Type

    conf

  • DOI
    10.1109/AUTEST.1996.547671
  • Filename
    547671