DocumentCode :
2531165
Title :
Pre-breakdown charge trapping in ESD stressed thin MOS gate oxides
Author :
Teh, G.L. ; Chim, W.K.
Author_Institution :
Centre for Integrated Circuit Failure Anal. & Reliability, Nat. Univ. of Singapore, Singapore
fYear :
1997
fDate :
21-25 Jul 1997
Firstpage :
156
Lastpage :
161
Abstract :
A change in the pre-breakdown trap generation under constant voltage stressing (CVS) was observed in thin oxides subjected to positive ESD pulses applied to the gate electrode. Results show that ESD pulses will create both positive and neutral traps, the latter being highly susceptible to electron trapping. It was also found that the damage in oxides subjected to low-level ESD events (i.e. number of ESD pulses less than 20) can be annealed out electrically. These annealed oxides show electrical characteristics that are identical to that of a non-ESD-stressed oxide
Keywords :
MIS devices; annealing; electron traps; electrostatic discharge; ESD pulse; MOS gate oxide; SiO2; annealing; constant voltage stress; damage; electrical characteristics; electron trap generation; pre-breakdown charge trapping; Annealing; Current measurement; Degradation; Electron traps; Electrostatic discharge; MOS capacitors; Power transmission lines; Silicon compounds; Stress; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical & Failure Analysis of Integrated Circuits, 1997., Proceedings of the 1997 6th International Symposium on
Print_ISBN :
0-7803-3985-1
Type :
conf
DOI :
10.1109/IPFA.1997.638186
Filename :
638186
Link To Document :
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