New design technology for EEPROM memory cells with 10 million write/erase cycling endurance

The authors describe a novel design technology for improving the write/erase cycling endurance characteristics for EEPROM (electrically erasable PROM) memory cells with self-aligned double polysilicon stacked structure. In this device, the source n/sup +/ region is located within the depletion region of the surface channel area when high voltage is applied to the drain with the source left floating. It is confirmed experimentally that the endurance of the newly designed memory cell using a 0.5- mu m design rule can be more than 10/sup 7/ write/erase cycles. This memory cell has superior potential for application to 64-Mb flash or 4-Mb full-featured EEPROMs.<>