New design technology for EEPROM memory cells with 10 million write/erase cycling endurance

Author

Endoh, T. ; Shirota, R. ; Tanaka, Y. ; Nakayama, R. ; Kirisawa, R. ; Aritome, S. ; Masuoka, F.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1989

fDate

3-6 Dec. 1989

Firstpage

599

Lastpage

602

Abstract

The authors describe a novel design technology for improving the write/erase cycling endurance characteristics for EEPROM (electrically erasable PROM) memory cells with self-aligned double polysilicon stacked structure. In this device, the source n/sup +/ region is located within the depletion region of the surface channel area when high voltage is applied to the drain with the source left floating. It is confirmed experimentally that the endurance of the newly designed memory cell using a 0.5- mu m design rule can be more than 10/sup 7/ write/erase cycles. This memory cell has superior potential for application to 64-Mb flash or 4-Mb full-featured EEPROMs.<>

Keywords

EPROM; MOS integrated circuits; integrated circuit technology; integrated memory circuits; 0.5 micron; 4 Mbit; 64 Mbit; EEPROM memory cells; design technology; electrically erasable PROM; flash memory application; polycrystalline Si; self-aligned double polysilicon stacked structure; source n/sup +/ region; write/erase cycling endurance; Acceleration; Avalanche breakdown; Cathodes; Character generation; EPROM; Electron traps; Hot carriers; Stress; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1989.74352

Filename

74352