A reusable pseudo-random verification environment for complex digital designs: The SpaceWire interface case study

In the last decades, the complexity of embedded systems has been increasing continuously thanks to the industrial improvements in nanometric CMOS technologies, that allow the integration of hundreds of Intellectual Property cores on a single chip die. This process has been favored by the trend towards design of reusable and configurable components that can be utilized across different chips. In such a scenario, verification has become an extremely demanding step in the design flow, and Electronic Design Automation companies are developing tools that bring rapid development, reusability concepts and automation techniques in the world of functional verification too. This work faces the issue of providing an automated and configurable verification environment for a SpaceWire interface: the architecture is described and a comparison with standard verification methodologies is provided.