Title :
Building in reliability during ESD design layout
Author_Institution :
Intel Technol., Penang, Malaysia
Abstract :
Building in reliability during ESD design layout is key to the success of product design and development. Due to the limitations of automated layout checkers for ESD, knowledge of fundamental device physics, ESD and stress environments are essential
Keywords :
circuit layout CAD; electrostatic discharge; integrated circuit design; integrated circuit layout; integrated circuit reliability; product development; ESD design layout; automated layout checkers; fundamental device physics; product design; product development; reliability; stress environments; Buildings; Circuits; Clocks; Electrostatic discharge; Failure analysis; Physics; Product design; Reliability theory; Stress; Variable structure systems;
Conference_Titel :
Physical & Failure Analysis of Integrated Circuits, 1997., Proceedings of the 1997 6th International Symposium on
Print_ISBN :
0-7803-3985-1
DOI :
10.1109/IPFA.1997.638192
