AES as stream cipher on a small FPGA

Author

Good, Tim ; Benaissa, Mohammed

Author_Institution

Dept. of Electr. & Electron. Eng., Sheffield Univ.

fYear

2006

fDate

21-24 May 2006

Abstract

This paper presents a very low area design for the advanced encryption standard (AES) capable of functioning in three of its feedback modes to provide flexible support for its use as a stream cipher. The architecture is based around an 8-bit application specific instruction processor (ASIP) and includes UARTs to support asynchronous serial I/O. The entire design fits within the smallest Xilinx Spartan-II FPGA (XC2S15), occupying 174 slices and two block memories. The design achieves a throughput of 2.3 Mbps with a 70MHz clock in OFB, CTR and CFB modes. The size is approximately 27% smaller than a comparable RC4 design

Keywords

application specific integrated circuits; cryptography; field programmable gate arrays; 2.3 Mbit/s; 70 MHz; AES; CFB mode; CTR mode; FPGA; OFB mode; UART; advanced encryption standard; application specific instruction processor; asynchronous serial I/O; low area design; stream cipher; Application specific processors; Books; Code standards; Cryptography; Design engineering; Feedback; Field programmable gate arrays; Process design; Standards development; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692639

Filename

1692639