An analog storage cell with 5e/sup -//sec leakage

The voltage droop rate of capacitive analog storage cells is typically limited by the off state leakage of a single MOS switch. Past low-leakage switch designs have assumed that subthreshold conduction and drain-to-bulk diode leakage dominate other effects. However, recent measurements of MOS leakage in a 1.5mum CMOS process have revealed a third important mechanism that can contribute significant leakage. It has been shown that incorporating a novel MOS switch topology into a high-accuracy switched-capacitor storage cell can minimize all of the experimentally observed leakages, achieving 10aA average leakage in a 1.5mum process. This paper presents new experimental data from cells fabricated in a 0.5pm process that exhibit 0.8aA (5e^-/sec) average leakage, a 100times reduction over the leading alternative cell in the literature. This implies that with a 1pF storage capacitor and a 3.3V supply, this cell can store a 12-bit accurate voltage for 14.5 minutes and an 8-bit accurate voltage for 3.9 hours. The leakage reduction between the 1.5mum and 0.5mum implementations appears to be reasonable based on simple scaling arguments