Title :
A new E(E)PROM technology with a TiSi/sub 2/ control gate
Author :
Vollebregt, F. ; Cuppens, R. ; Druyts, F. ; Lemmen, G. ; Verberne, F. ; Solo, J.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
A single polysilicon CMOS process optimized for the production of nonvolatile memory embedded in VLSI logic is described. The process differs from conventional approaches in two aspects: it uses a TiSi/sub 2/ control gate instead of a thicker polysilicon layer, and the isolation between the polysilicon floating gate and TiSi/sub 2/ control gate is a single LPCVD (low-pressure chemical-vapor-deposited) oxynitride layer instead of the complex oxide-nitride-oxide stack or high-temperature thermal oxide. EEPROM (electrically erasable PROM) cells and flash EEPROM cells with TiSi/sub 2/ control gates and an oxynitride isolation were fabricated in the same process and show excellent endurance and retention characteristics. The technology, which is also suitable for embedded EPROM (electrically programmable ROM) has been developed as a simple, modular addition to a 5-V, double-metal salicided, 1- mu m CMOS logic process.<>
Keywords :
CMOS integrated circuits; EPROM; integrated circuit technology; integrated memory circuits; titanium compounds; LPCVD oxynitride layer; TiSi/sub 2/ control gate; VLSI logic embedded memory; electrically erasable PROM; embedded EPROM; endurance characteristics; flash EEPROM cells; low-pressure chemical-vapor-deposited; nonvolatile memory; oxynitride isolation; polycrystalline Si; polysilicon CMOS process; polysilicon floating gate; retention characteristics; CMOS logic circuits; CMOS process; CMOS technology; Chemical processes; EPROM; Nonvolatile memory; Optimized production technology; PROM; Thickness control; Very large scale integration;
Conference_Titel :
Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1989.74354
