A new E(E)PROM technology with a TiSi/sub 2/ control gate

A single polysilicon CMOS process optimized for the production of nonvolatile memory embedded in VLSI logic is described. The process differs from conventional approaches in two aspects: it uses a TiSi/sub 2/ control gate instead of a thicker polysilicon layer, and the isolation between the polysilicon floating gate and TiSi/sub 2/ control gate is a single LPCVD (low-pressure chemical-vapor-deposited) oxynitride layer instead of the complex oxide-nitride-oxide stack or high-temperature thermal oxide. EEPROM (electrically erasable PROM) cells and flash EEPROM cells with TiSi/sub 2/ control gates and an oxynitride isolation were fabricated in the same process and show excellent endurance and retention characteristics. The technology, which is also suitable for embedded EPROM (electrically programmable ROM) has been developed as a simple, modular addition to a 5-V, double-metal salicided, 1- mu m CMOS logic process.<>