• DocumentCode
    2531930
  • Title

    Asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half micron n-MOSFET design for reliability and performance

  • Author

    Buti, T.N. ; Ogura, S. ; Rovedo, N. ; Tobimatsu, K. ; Codella, C.F.

  • Author_Institution
    IBM East Fishkill Lab., Hopewell Junction, NY, USA
  • fYear
    1989
  • fDate
    3-6 Dec. 1989
  • Firstpage
    617
  • Lastpage
    620
  • Abstract
    A novel asymmetrical n-MOSFET device structure has been developed which is suitable, in terms of reliability and performance, for scaling down to the sub-quarter-micron level, without reduction of the supply voltage below 3.5 V. In this structure (HS-GOLD), large-tilt implantation is used to form the gate-overlapped lightly doped drain (GOLD) region at the drain electrode only. A halo (punch-through stopper) is used at the source, but not at the drain. Superior hot-carrier reliability and high punch-through resistance are obtained using this device structure. A reliability-limited supply voltage at 4.2 V is obtained for HS-GOLD n-MOSFETs with effective channel lengths as short as 0.25 mu m. High punch-through resistance is achieved without extreme scaling of S-D (source-drain) junctions and gate oxide (120 AA). The threshold roll-off characteristics suggest that this n-MOSFET structure can be designed with about 0.3 mu m shorter channel length (L/sub eff/=0.15 mu m) while maintaining the 3.5-V supply voltage. Reliable operation of 0.15- mu m n-MOSFETs at 3.5-V supply voltage using the proposed device structure is demonstrated by 2D simulation.<>
  • Keywords
    MOS integrated circuits; circuit reliability; hot carriers; insulated gate field effect transistors; integrated circuit technology; 0.15 micron; 0.25 micron; 2D simulation; 3.5 V; 4.2 V; LDD; asymmetrical n-MOSFET device structure; channel lengths; deep subhalf micron device; gate-overlapped lightly doped drain; halo source GOLD drain; hot-carrier reliability; large-tilt implantation; punch-through resistance; punch-through stopper; reliability-limited supply voltage; scaling down; submicron devices; threshold roll-off characteristics; Boron; Doping profiles; Fabrication; Gold; Hot carriers; Implants; MOSFET circuits; Metallization; Silicides; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
  • Conference_Location
    Washington, DC, USA
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-0817-4
  • Type

    conf

  • DOI
    10.1109/IEDM.1989.74356
  • Filename
    74356