Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking

Author

Senger, Robert M. ; Marsman, Eric D. ; Carichner, Gordon A. ; Kubba, Sundus ; McCorquodale, Michael S. ; Brown, Richard B.

Author_Institution

Michigan Univ., Ann Arbor, MI

fYear

2006

fDate

21-24 May 2006

Lastpage

778

Abstract

A low-latency, HDL-synthesizable dynamic clock frequency controller is presented as a time-efficient alternative to full-custom implementations. Frequency division of a fully integrated hybrid temperature-compensated LC oscillator (TC-LCO) and ring oscillator clock reference avoids PLL locking delays to enable low-latency, hazard-free frequency selection on an actively running CPU. Fabricated in 0.18mum CMOS as part of a low-power SoC microsystem, the circuit dissipates 480muW at 1.8V

Keywords

CMOS integrated circuits; clocks; low-power electronics; oscillators; phase locked loops; reference circuits; 0.18 micron; 1.8 V; 480 muW; PLL locking delays; SoC microsystem; clock frequency controller; frequency division; phase locked loops; ring oscillator clock reference; self-referenced hybrid clocking; temperature-compensated LC oscillator; Central Processing Unit; Circuits; Clocks; Costs; Delay; Dynamic voltage scaling; Embedded system; Frequency conversion; Phase locked loops; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692700

Filename

1692700