A low power, transverse analog FIR filter for feed forward equalization of gigabit Ethernet

An analog feed forward error equalizer (AFFE) is described that cancels precursor intersymbol interferences (ISI) in the front end of gigabit Ethernet on twisted pair interfaces. Forward equalizing in analog domain not only reduces the complexity and area of digital forward equalizer, but also leads to lower power consumption and higher speed. The proposed equalizer, based on five taps discrete time filtering, is designed in a 0.18mum CMOS technology. The design operates at 125MHz while consuming 38mW from a 1.8V supply. The low power and high speed design is achieved by implementation of each filter tap only by an improved Gilbert cell instead of using a multiplier for each bit of the filter tap which consumes more area and power and affected by switches noise and clock jitter too. Moreover S/H power and speed requirements are relaxed by using a redundant S/H and an additional clocking phase