Performance enhancement in the associative processing of floating point numbers using multi-core superscalar architecture

The necessity for high speed computation has motivated the development of a high performance processor for floating point computations. In this paper we examine, changes in the performance of a floating-point operation with respect to the number of processing units in case of a super scalar architecture. The prototype of the processors has been realized and studied on an FPGA. Our experimental results reveal that the performance of the floating-point unit not only depends on the number of processing units but also on the instruction level parallelism. Moreover, the percentage utilization of the combinational logic blocks of the FPGA has been studied under different numbers of cores on the chip. Multi-core architectures can be identified by how the individual cores are connected and the ways in which they access memory.